Integrated circuit (IC) memory devices allow large amounts of data to be stored in relatively small physical packages. One such device is a random access memory (RAM). A RAM comprises a plurality of memory cells, each of which is accessible by at least one data line commonly referred to as a "bit line." As data is written into and read out of a memory cell, the voltage appearing on the respective bit line may alternate between high and low values.
According to previously developed techniques, in order to provide faster operation for a RAM, an equilibration circuit is coupled to one end of a bit line. The equilibration circuit pre-charges the voltage on the bit line to a predetermined value, which is typically midway between the high and low voltage values. This pre-charging to a mid-level value allows the voltage on the bit line to be moved more rapidly to either the high value or the low value, thereby increasing the speed at which data is written into or read out of a memory cell. Nonetheless, because the portion of a bit line furthest from the equilibration circuit is charged more slowly than the portion closest to the equilibration circuit, a certain amount of delay is associated with pre-charging the far end of the bit line up to the desired mid-level value. For longer bit lines, such a time delay can be significant.